An E cient Method for the Self - Consistent Electro - Thermal Simulation and its Integration into a CAD Framework

In this paper we address the chip-level thermal simulation problem. Our work is based on some early results treating electro-thermal problems on circuit level 11, 22. The developed electro-thermal simulation package has been integrated under Cadence DFWII Opus. Due to its relatively low CPU need this package can be used as a thermal veriication tool of layouts of analog circuits. In our approach for the self-consistent electro-thermal simulation we apply the idea of mapping the thermal networks into an electrical equivalent. In this way the entire electro-thermal simulation problem can be treated simultaneously, b y usual circuit simulation algorithms. It requires that the usual semiconductor device models of a SPICE-like simulator should be completed with the description of the mutual electro-thermal coupling eeects, including the @P=@U and @I=@T thermal transconductances. Once we h a v e an electro-thermal circuit simulation program we h a v e to generate the lumped thermal model of the IC chip itself. For the steady-state case this is a thermal resistance network with device-to-device and device-to-ambient thermal resistances. For a given physical arrangement this network is an exact model of the distributed thermal system. The usual netlist extraction is completed such, that the lumped element thermal model of the IC chip is also generated. The extraction of the thermal sub-model is based on the layout of the dissipating devices. The necessary calculations are performed by the THERMANAL thermal simulation program 3. For the simultaneous electro-thermal simulation we use the TRANS-TRAN program 33, which uses the electro-thermal netlist provided by the extended netlist extraction. The circuit simulation results in the exact dissipation values of the active devices, re-ecting the self-consistent solution. These are used in a nal thermal simulation which provides the 2D temperature proole over the chip surface. The device temperatures calculated by the thermal simulation tool and the ones calculated by the circuit sim-ulator are identical. T h us, using the electro-thermal circuit simulator with a thermal pre-processing step, an eeective, self-consistent steady-state solution of the thermo-electrical problems of integrated circuits is possible. Our simulation method has been implemented under Cadence DFWII Opus conngured for the ecpd10 process of ES2. The nal temperature distribution maybe looked at from Opus, see the gure. The implemented method has the following advantages: i No inner iteration loop invoking the circuit and thermal simulation tools is needed. ii The number of thermal simulations is N + 1, where …